Implantations for Forming Source/Drain Regions of Different Transistors

ABSTRACT

A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 16/416,792, filed May 20, 2019 entitled “Implantations for Forming Source/Drain Regions of Different Transistors,” which application is a continuation of U.S. patent application Ser. No. 15/598,825, entitled “Implantations for Forming Source/Drain Regions of Different Transistors,” filed on May 18, 2017, now U.S. Pat. No. 10,297,602, issued May 21, 2019, which applications are incorporated herein by reference.

BACKGROUND

Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, three-dimensional transistors such as a Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. Although existing FinFET devices and methods of fabricating FinFET devices have been generally adequate for their intended purposes, more problems emerge with the increasing downscaling of circuits. For example, the FinFETs for different circuits such as core (logic) circuits, Static Random Access Memory (SRAM) circuits, and Input-Output devices may face different problems with the increasing downscaling of integrated circuits, which problems were not observed before.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 through 15 illustrate the cross-sectional views and perspective views of intermediate stages in the formation of Fin Field-Effect Transistors (FinFETs) in accordance with some embodiments.

FIG. 16 illustrates the layout of some circuits in accordance with some embodiments.

FIG. 17 illustrates a process flow for forming FinFETs in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Transistor and the methods of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the transistors are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In the illustrated exemplary embodiments, the formation of Fin Field-Effect Transistors (FinFETs) is used as an example to explain the concepts of the present disclosure. Planar transistors may also adopt the concept of the present disclosure.

FIG. 16 illustrates an exemplary layout of circuits in device regions 100 and 200. Throughout the description, device region 100 is a region in which long-channel transistors are formed, and device region 200 is a region in which short-channel transistors are formed. It is appreciated that the terms “long-channel” and “short-channel” are relative to each other. The long-channel transistors have channels longer than the channels of short channel transistors. In accordance with some embodiments of the present disclosure, the long-channel device region 100 include Static Random Access Memory (SRAM) cells or Input-Output (IO) circuits, and the transistors therein are long-channel transistors. The short-channel device region 200 may include logic circuits/transistors (sometimes referred to as core circuits/transistors), and the transistors therein are short-channel transistors. For example, FIG. 16 illustrates an SRAM cell 102 in device region 100. In accordance with alternative embodiments, device region 100 includes an IO transistor(s). SRAM cell 102 includes p-type transistors PU1 and PU2 formed in an N-well, and n-type transistors PD1, PD2, PG1, and PG2 formed in P-wells. Transistors PU1, PU2, PD1, PD2, PG1, and PG2 are formed based on active regions (which may be semiconductor fins) 104A, 104B, 104C, and 104D and gate electrodes 106A, 106B, 106C, and 106D. Transistor 202 is in device region 200, and is formed based on active regions (which may also be semiconductor fins) 204 and gate electrodes 206. Transistor 202 may be a p-type transistor or an n-type transistor.

In accordance with some embodiments of the present disclosure, as shown in FIG. 15, the channel-length Lg2 of the short-channel device is smaller than about 30 nm, and the channel-length Lg1 of the long-channel device is greater than about 60 nm. The ratio Lg1/Lg2 may be greater than about 2.0 in accordance with some embodiments, and may be in the range between about 2 and about 10.

FIGS. 1 through 15 illustrate the cross-sectional views and perspective views of intermediate stages in the formation of transistors in accordance with some embodiments of the present disclosure. The steps shown in FIGS. 1 through 15 are also reflected schematically in the process flow 300 shown in FIG. 17. The formed transistors include a long-channel transistor (such as a long-channel FinFET as an example) in device region 100 and a short-channel transistor (such as a short-channel FinFET as an example) in device region 200. In accordance with some exemplary embodiments of the present disclosure, the long-channel transistor and the short-channel transistor in device regions 100 and 200, respectively, are of a same conductivity type, and may be both p-type transistors or both n-type transistors. For example, the long-channel transistor formed in device region 100 may be a p-type transistor such as transistor PU1 or PU2 in FIG. 16, an n-type transistor such as transistor PD1, PD2, PG1, or PG2 in FIG. 16, or a p-type or n-type transistor in an IO circuit. The short-channel transistor formed in device region 200 may be either a p-type transistor or an n-type transistor, with the layout illustrated in FIG. 16.

FIG. 1 illustrates a perspective view of an initial structure. The initial structure includes wafer 10, which further includes substrate 20. Substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. Substrate 20 may be doped with a p-type or an n-type impurity. Isolation regions 22 such as Shallow Trench Isolation (STI) regions may be formed to extend into substrate 20. The portions of substrate 20 between neighboring STI regions 22 are referred to as semiconductor strips 124 and 224, which are in device regions 100 and 200, respectively.

STI regions 22 may include a liner oxide (not shown). The liner oxide may be formed of a thermal oxide formed through a thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). STI regions 22 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like.

Referring to FIG. 2, STI regions 22 are recessed, so that the top portions of semiconductor strips 124 and 224 protrude higher than the top surfaces 22A of the neighboring STI regions 22 to form protruding fins 124′ and 224′. The respective step is illustrated as step 302 in the process shown in FIG. 17. The etching may be performed using a dry etching process, wherein NH₃ and NF₃ are used as the etching gases. During the etching process, plasma may be generated. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of STI regions 22 is performed using a wet etch process. The etching chemical may include diluted HF, for example.

Referring to FIG. 3, dummy gate stacks 130 and 230 are formed on the top surfaces and the sidewalls of protruding fins 124′ and 224′, respectively. The respective step is illustrated as step 304 in the process shown in FIG. 17. Dummy gate stacks 130 may include gate dielectrics 132 and dummy gate electrodes 134 over dummy gate dielectrics 132. Dummy gate stacks 230 may include gate dielectrics 232 and dummy gate electrodes 234 over dummy gate dielectrics 232. Dummy gate electrodes 134 and 234 may be formed, for example, using polysilicon, and other materials may also be used. Each of dummy gate stacks 130 and 230 may also include one (or a plurality of) hard mask layers 136 and 236. Hard mask layers 136 and 236 may be formed of silicon nitride, silicon carbo-nitride, or the like. Each of dummy gate stacks 130 and 230 crosses over a single one or a plurality of protruding fins 124′ and 224, respectively. Dummy gate stacks 130 and 230 may also have lengthwise directions perpendicular to the lengthwise directions of the respective protruding fins 124′ and 224′, respectively.

Next, gate spacers 138 and 238 are formed on the sidewalls of dummy gate stacks 130 and 230, respectively. In the meantime, fin spacers (not shown) may also be formed on the sidewalls of protruding fins 124′ and 224′ respectively. In accordance with some embodiments of the present disclosure, gate spacers 138 and 238 are formed of a dielectric material(s) such as silicon carbon-oxynitride (SiCN), silicon nitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

In accordance with some embodiments, each of gate spacers 138 includes a low-k dielectric layer 138A and a non-low-k dielectric layer 138B (refer to FIG. 6B), with each of layers 138A and 138B formed through a blanket deposition step followed by an anisotropic etching step. Low-k dielectric layer 138A may be formed of a low-k dielectric material having a dielectric constant (k value) lower than about 3.0, which may be formed of SiON or SiOCN, with pores formed therein in order to reduce its k value. Non-low-k dielectric layer 138B may be formed of silicon nitride, for example. Gate spacers 238 have the same structure as gate spacers 138, and may include layers 238A and 238B formed of the same materials as layers 138A and 138B, respectively.

An etching step (referred to as source/drain recessing hereinafter) is then performed to etch the portions of protruding fins 124′ and 224′ (and the underlying portions of strips 124 and 224) that are not covered by dummy gate stacks 130 and 230 and gate spacers 138 and 238, resulting in the structure shown in FIG. 4. The recessing may be anisotropic, and hence the portions of fins 124′ and 224′ directly underlying the respective dummy gate stack 130/230 and gate spacers 138/238 are protected, and are not etched. The top surfaces of the recessed semiconductor strips 124 and 224 may be lower than the top surfaces of the adjacent STI regions 22 in accordance with some embodiments. Recesses 140 and 240 are accordingly formed between STI regions 22. The recessing in device regions 100 and 200 may be performed in a common etching process or in separate processes, and the depths of recesses 140 may be equal to or different from the depths of recesses 240.

Next, epitaxy regions (source/drain regions) are formed by selectively growing a semiconductor material in recesses 140 and 240 simultaneously (or separately), resulting in the structure in FIG. 5. The respective step is illustrated as step 306 in the process shown in FIG. 17. In accordance with some exemplary embodiments, epitaxy regions 142 and 242 include silicon germanium or silicon. Depending on whether the resulting FinFETs are p-type FinFETs or n-type FinFETs, a p-type or an n-type impurity may be in-situ doped with the proceeding of the epitaxy. For example, when the resulting FinFETs are p-type FinFETs, silicon germanium boron (SiGeB) may be grown. Conversely, when the resulting FinFETs are n-type FinFETs, silicon phosphorous (SiP) or silicon carbon phosphorous (SiCP) may be grown. The concentration of the in-situ doped p-type or n-type impurity may be a higher than about 1×10²⁰/cm³, and may be between about 1×10²⁰/cm³, and about 2×10²¹/cm³ in accordance with some embodiments. In accordance with alternative embodiments of the present disclosure, epitaxy regions 142 and 242 are formed of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multi-layers thereof. After recesses 140 and 240 are filled with the epitaxy semiconductor material, the further epitaxial growth of epitaxy regions 142 and 242 causes epitaxy regions 142 and 242 to expand horizontally, and facets may be formed. Neighboring epitaxy regions 142 and 242 may or may not be joined. Throughout the description, epitaxy regions 142 and 242 are referred to as source/drain regions.

Referring to FIG. 6A, photo resist 243 is formed and patterned. Device region 200 is covered by photo resist 243, and device region 100 is not covered. Next, an implantation is performed to implant a p-type impurity or an n-type impurity. The respective step is illustrated as step 308 in the process shown in FIG. 17. The implantation is referred to as after-epi source/drain implantation. The implantation is represented by arrows 139. The implanted impurity has the same conductivity type as the in-situ doped impurity introduced in the step shown in FIG. 5. For example, if the resulting FinFETs in device regions 100 and 200 are of p-type, the implanted impurity is also p-type, and if the resulting FinFETs in device regions 100 and 200 are of n-type, the implanted impurity is also n-type. As a result of the implantation, the impurity concentration in source/drain regions 142 may be increased by two times to five times the impurity concentration of the in-situ doped impurity.

FIG. 6B illustrates the cross-sectional views of the structure shown in FIG. 6A, wherein the cross-sectional view includes the cross-sectional views obtained from the vertical plane containing line A-A and the vertical plane containing line B-B in FIG. 6A. In accordance with some embodiments, the implantation is performed vertically. The likely positions of the bottoms of the implanted regions 145 are marked as 145′, which may be higher than, at the same level as, or lower than, the bottoms of epitaxy regions 142. Source/drain regions 242 are not implanted by any after-epi implantation due to photo resist 243. Since the implantation is performed using the same mask (gate stack 130 and spacers 138) as the etching shown in FIG. 4, the implanted regions 145 extend to both the inner edges and outer edges of source/drain regions 142. Phone resist 243 is removed after the implantation.

FIG. 7A illustrates a perspective view of forming Contact Etch Stop Layers (CESLs) 147 and 247 and Inter-Layer Dielectric (ILD) 46. The respective step is illustrated as step 310 in the process shown in FIG. 17. In accordance with some embodiments of the present disclosure, CESLs 147 and 247 are formed of silicon nitride, silicon carbo-nitride, or the like. CESLs 147 and 247 may be formed using a conformal deposition method such as ALD or CVD, for example. ILD 46 is formed over CESLs 147 and 247, and may be formed using, for example, FCVD, spin-on coating, CVD, or the like. ILD 46 may be formed of Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetra Ethyl Ortho Silicate (TEOS) oxide, or the like. A planarization such as Chemical Mechanical Polish (CMP) or grinding may be performed to level the top surfaces of ILD 46, dummy gate stacks 130 and 230, and gate spacers 138 and 238 with each other.

FIG. 7B illustrates the cross-sectional views of the structure shown in FIG. 7A, with the cross-sectional views being obtained from the vertical plane containing line A-A and the vertical plane containing line B-B in FIG. 7A. After the structure shown in FIGS. 7A and 7B is formed, the dummy gate stacks 130 and 230 including hard mask layers 136 and 236, dummy gate electrodes 134 and 234, and dummy gate dielectrics 132 and 232 are replaced with metal gates and replacement gate dielectrics, as shown in FIGS. 8 and 9. In FIGS. 6B, 7B, and FIGS. 8 through 15, the top surfaces 122A and 222A of STI regions 22 are illustrated, and protruding fins 124′ and 224′ protrude higher than top surfaces 122A and 222A, respectively.

To form the replacement gates, hard mask layers 136 and 236, dummy gate electrodes 134 and 234, and dummy gate dielectrics 132 and 232 as shown in FIGS. 7A and 7B are removed, forming openings 148 and 248 as shown in FIG. 8. The respective step is illustrated as step 312 in the process shown in FIG. 17. The top surfaces and the sidewalls of protruding fins 124′ and 224′ are exposed to openings 148 and 248, respectively.

Next, referring to FIG. 9, replacement gate stacks 150 and 250 are formed, and hard mask 152 and 252 are formed over gate stacks 150 and 250, respectively. The respective step is illustrated as step 314 in the process shown in FIG. 17. Replacement gate stacks 150 and hard mask 152 are between opposite gate spacers 138, and gate stacks 250 and hard mask 252 are between opposite gate spacers 238. Additional gate spacers 151 and 251 may (or may not) be formed in openings 148 and 248 (FIG. 8), respectively. The formation process is briefly discussed as follows.

In accordance with some embodiments, gate spacers 151 and 251 are formed lining the sidewalls of openings 151 and 251 first. In accordance with alternative embodiments, gate spacers 151 and 251 are not formed. To form gate spacers 151 and 251, a blanket gate spacer layer(s) may be formed, for example, using a deposition method such as ALD or CVD. The blanket gate spacer layer is conformal. In accordance with some embodiments of the present disclosure, the gate spacer layer is formed of silicon nitride (SiN), SiC, SiON, or the like. Gate spacers 151 and 251 separate the subsequently formed metal gates farther away from source/drain regions 142 and 242, and the possibility of leakage and electrical shorting between them are reduced. Gate spacers 151 may include low-k dielectric layer 151A, which may be formed of porous SiON, and dielectric layer 151B, which may be a high-k dielectric layer or has a k value substantially equal to 3.9 (and hence is neither a high-k nor a low-k dielectric material). The k value of low-k dielectric layer 151A may be between about 3.0 and about 3.5, for example. Gate spacers 251 may have the same structure as gate spacers 151, and hence may also include dielectric layer 251A formed of a same material as dielectric layer 151A, and dielectric layer 251B formed of a same material as dielectric layer 151B.

As also shown in FIG. 9, gate stacks 150 and 250 include gate dielectrics 154/156 and 254/256, which extend into openings 148 and 248, respectively. In accordance with some embodiments of the present disclosure, the gate dielectrics include Interfacial Layers (ILs) 154 and 254, which are formed on the exposed surfaces of protruding fins 124′ and 224′, respectively. Each of ILs 154 and 254 may include an oxide layer such as a silicon oxide layer, which is formed through the thermal oxidation of protruding fins 124′ and 224′, a chemical oxidation process, or a deposition process. The gate dielectrics may also include high-k dielectric layers 156 and 256 over the corresponding ILs 154 and 254. High-k dielectric layers 156 and 256 may be formed of a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, and sometimes as high as 20 or higher. High-k dielectric layers 156 and 256 are formed as conformal layers, and extend on the sidewalls of protruding fins 124′ and 224′ and the sidewalls of gate spacers 138/151 and 238/251, respectively. In accordance with some embodiments of the present disclosure, high-k dielectric layers 156 and 256 are formed using ALD or CVD.

Further referring to FIG. 9, metal-containing conductive layers 162 and 262 are formed through deposition. The deposition may be performed using a conformal deposition method such as ALD or CVD, so that the horizontal thickness of the horizontal portions and vertical thickness of the vertical portions of metal-containing layer 162/262 (and each of sub-layers) have thicknesses substantially equal to each other. For example, the horizontal thickness and the vertical thickness may have a difference smaller than about 20 percent or 10 percent of either of the horizontal thickness and the vertical thickness.

Each of metal-containing layers 162 and 262 includes at least one layer, or may include a plurality of layers (not shown) formed of different materials. The corresponding layers in metal-containing conductive layers 162 and 262 may be formed in common deposition processes or separate deposition processes. The materials of the layers in metal-containing layers 162 and 262 may include work-function metals selected according to whether the respective FinFETs are n-type FinFETs or p-type FinFETs. For example, when the FinFETs are n-type FinFETs, each of metal-containing layers 162 and 262 may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and an Al-based layer (formed of, for example, TiAl, TiAlN, TiAlC, TaAlN, or TaAlC), respectively. When the FinFETs are p-type FinFETs, each of metal-containing layers 162 and 262 may include a TiN layer, a TaN layer, and another TiN layer, respectively. Layers 162 and 262 may also include two layers or more than three layers.

A filling metal is then filled over layers 162 and 262 to form metal regions 164 and 264. In accordance with some exemplary embodiments, the filling metal includes W, Cu, Co. Al, Ru, or alloys thereof. After metal regions 164 and 264 are deposited, a planarization step such as CMP or mechanical grinding is performed to remove excess portions of the deposited layers over the top surface of ILD 46, and hence gate stacks 150 and 250 are formed.

Next, gate stacks 150 and 250 are recessed to form recesses, followed by filling a dielectric material into the recesses to form hard masks 168 and 268. Another planarization step is then performed to level to the top surfaces of hard masks 168 and 268 with the top surface of ILD 46. Hard masks 168 and 268 may be dielectric hard masks formed of silicon nitride, silicon oxynitride, silicon oxy-carbide, or the like.

In a subsequent step, as shown in FIG. 10, ILD 46 and CESL 147 and 247 are etched to form contact openings 170 and 270. The respective step is illustrated as step 316 in the process shown in FIG. 17. Source/drain regions 142 and 242 are thus revealed. FIG. 11 illustrates the formation of photo resist 172 to cover device region 100, while leaving device region 200 uncovered. Next, an implantation is performed to implant a p-type impurity or an n-type impurity, which has the same conductivity type as the after-epi implantation as shown in FIGS. 6A and 6B. The implantation shown in FIG. 11 is referred to as after-contact source/drain implantation. The respective step is illustrated as step 318 in the process shown in FIG. 17. The implantation is represented by arrows 273. As a result of the implantation, the impurity concentration in the implanted regions 245 may be increased by two times to five times the impurity concentration of the in-situ doped impurity. The implantation may be performed vertically.

As shown in FIG. 11, contact openings 270 are spaced apart from gate spacers 238 by horizontal distance D1. Distance D1 has a non-zero value, which may be between about 5 nm and about 10 nm. Accordingly, the respective implanted regions 245 are spaced apart from the channel region of the respective transistor farther than the implanted regions 145 formed by the after-epi implantation as shown in FIGS. 6A and 6B. The likely positions of the bottoms of implanted regions 245 are marked as 245′, which may be higher than, at the same level as, or lower than, the bottoms of epitaxy regions 242. Source/drain regions 142 are not implanted by any after-contact implantation due to photo resist 243. Photo resist 243 is then removed, resulting in the structure shown in FIG. 12.

FIG. 13 illustrates the formation of source/drain silicide regions 174 and 274 and source/drain contact plugs 182 and 282. The respective step is illustrated as step 320 in the process shown in FIG. 17. In accordance with some embodiments, metal layers 176 and 276 (titanium layers, for example) are deposited as a blanket layer, followed by a nitridation process on the top portion of metal layers 176 and 276 to form metal nitride layers 178 and 278. The bottom portion of metal layers 176 and 276 are not nitridated. Next, an anneal (which may be rapid thermal anneal) is performed to react the metal layers 176 and 276 with the top portions of source/drain regions 142 and 242 to form silicide regions 174 and 274. The portions of metal layers 176 and 276 on the sidewalls of ILD 46 are not reacted. Metal regions 180 and 280 are then formed, for example, by filling tungsten, cobalt, or the like, followed by a planarization to remove excess materials, resulting in lower source/drain contact plugs 182 and 282. Contact plug 182 includes layers 176, 178, and 180, and contact plug 282 including layers 276, 278, and 280. Long-channel transistor 199 and short-channel transistor 299 are thus formed.

Referring to FIG. 14, etch stop layer 84 is formed. In accordance with some embodiments, etch stop layer 84 is formed of SiN, SiCN, SiC, SiOCN, or another dielectric material. The formation method may include PECVD, ALD, CVD, or the like. Next, ILD 86 is formed over etch stop layer 84. The material of ILD 86 may be selected from the same candidate materials (and methods) for forming ILD 46, and ILDs 46 and 86 may be formed of the same or different dielectric materials. In accordance with some embodiments, ILD 86 is formed using PECVD, FCVD, spin-on coating, or the like, and may include silicon oxide (SiO₂).

ILD 86 and etch stop layer 84 are etched to form openings (not shown). The etching may be performed using, for example, Reactive Ion Etch (RIE). In a subsequent step, as shown in FIG. 15, plugs/vias 188, 190, 288, and 290 are formed. In accordance with some embodiments of the present disclosure, plugs/vias 188, 190, 288, and 290 include barrier layers 92 and metal-containing material 94 over the barrier layers. In accordance with some embodiments of the present disclosure, the formation of plugs/vias 188, 190, 288, and 290 includes forming a blanket barrier layer 92 and a metal-containing material 94 over the blanket barrier layer, and performing a planarization to remove excess portions of the blanket barrier layer and the metal-containing material. Barrier layer 92 may be formed of a metal nitride such as titanium nitride or tantalum nitride. Metal-containing material 94 may be formed of tungsten, cobalt, copper, or the like. In accordance with some embodiments, dielectric contact spacers 196 and 296 are formed to encircle plugs/vias 188, 190, 288, and 290.

The embodiments of the present disclosure have some advantageous features. Since the transistor formed in device region 200 is a short-channel transistor, if the source/drain implantation is performed using after-epi implantation, the implanted impurity is closer to the channel, and is more likely to diffuse into the channel region to degrade the short-channel effect and Drain-Induced Barrier Lowering (DIBL) performance of the transistor. Accordingly, for the short-channel device in device region 200, after-contact implantation is performed, and after-epi implantation is not performed. Conversely, for the long-channel transistor in device region 100, for example, a SRAM transistor, the layout effect may cause the threshold voltage to be adversely increased. The after-epi implantation is closer to the channel of the respective transistor, and hence has the effect of reducing the threshold voltage and reducing channel resistance. Also, long-channel transistors suffer less from the short-channel effect and DIBL performance degradation caused by the diffusion of the implanted impurity into the channel region. In conventional processes, however, a source/drain implantation is performed simultaneously for long-channel transistors and short-channel transistors, and the device performance of long-channel transistors and short-channel transistors cannot be tuned.

In accordance with some embodiments of the present disclosure, a method includes forming a first gate stack on a sidewall and a top surface of a first portion of a first protruding fin, forming a second gate stack on a sidewall and a top surface of a first portion of a second protruding fin, etching a second portion of the first protruding fin and a second portion of the second protruding fin to form a first recess and a second recess, respectively, epitaxially growing a first source/drain region and a second source/drain region in the first recess and the second recess, respectively, and performing a first implantation on the first source/drain region without implanting the second source/drain region. After the first implantation, an ILD is formed to cover the first source/drain region and the second source/drain region. The method further includes forming a first contact opening and a second contact opening in the ILD to reveal the first source/drain region and the second source/drain region, and performing a second implantation on the second source/drain region without implanting the first source/drain region. The second implantation is performed through the second contact opening.

In accordance with some embodiments of the present disclosure, a method includes forming a first gate stack and a second gate stack on semiconductor regions, forming a first gate spacer on a sidewall of the first gate stack, forming a second gate spacer on a sidewall of the second gate stack, and forming a first source/drain region and a second source/drain region. The first source/drain region has an inner edge vertically substantially aligned to a sidewall of the first gate stack, and the second source/drain region has an inner edge substantially vertically aligned to a sidewall of the second gate stack. A first implantation is performed on the first source/drain region to generate a first implanted region, and the first implanted region has an inner edge vertically aligned to a sidewall of the first gate stack. An ILD is formed to cover the first source/drain region and the second source/drain region. A first contact opening and a second contact opening are formed in the ILD to reveal the first source/drain region and the second source/drain region. A second implantation is performed on the second source/drain region to generate a second implanted region. The second implanted region is spaced apart from the second gate spacer by a portion of the ILD.

In accordance with some embodiments of the present disclosure, a method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A structure comprising: a first transistor comprising: a first channel having a first channel length; a first gate stack on the first channel; a first gate spacer on a sidewall of the first gate stack; and a first doped region on a side of the first channel, wherein the first doped region is vertically aligned to a first outer edge of the first gate spacer; and a second transistor comprising: a second channel having a second channel length smaller than the first channel length; a second gate stack on the second channel; a second gate spacer on a sidewall of the second gate stack; and a second doped region on a side of the second channel, wherein the second doped region is laterally spaced apart from the second gate spacer.
 2. The structure of claim 1, wherein the first doped region and the second doped region are of a same conductivity type selected from p-type or n-type.
 3. The structure of claim 1, wherein the first transistor is in a static random access memory cell, and the second transistor is a logic transistor.
 4. The structure of claim 1, wherein both of the first transistor and the second transistor are p-type transistors.
 5. The structure of claim 1, wherein both of the first transistor and the second transistor are n-type transistors.
 6. The structure of claim 1, wherein: the first transistor comprises a first epitaxy semiconductor material different from a first material of the first channel, and the first doped region is in the first epitaxy semiconductor material and extends to edges of the first epitaxy semiconductor material; and the second transistor comprises a second epitaxy semiconductor material different from a second material of the second channel, and the second doped region is inside the second epitaxy semiconductor material, and is spaced apart from opposing edges of the second epitaxy semiconductor material.
 7. The structure of claim 1 further comprising: a first silicide region over the first doped region, wherein the first silicide region is laterally spaced apart from the first outer edge of the first gate spacer.
 8. The structure of claim 7 further comprising: a second silicide region over the second doped region, wherein the second doped region has a first inner edge spaced apart from a second outer edge of the second gate spacer, and wherein a second inner edge of the second silicide region is flush with the first inner edge.
 9. The structure of claim 1, wherein a ratio of the first channel length to the second channel length is greater than about 2.0.
 10. A structure comprising: a semiconductor substrate; a first transistor comprising: a first gate stack; a first gate spacer on a sidewall of the first gate stack; a first epitaxy region on a side of the first gate stack, wherein the first epitaxy region comprises a first lower portion having a first doping concentration of a conductive type, and a first upper portion having a second doping concentration of the conductivity type, wherein the second doping concentration is higher than the first doping concentrate, and wherein a first inner edge of the first upper portion is flushed with a first outer edge of the first gate spacer; and a first source/drain silicide region over and contacting the first epitaxy region, wherein the first source/drain silicide region is spaced apart from the first outer edge of the first gate spacer; and a second transistor comprising: a second gate stack; a second gate spacer on a sidewall of the second gate stack; a second epitaxy region on a side of the second gate stack, wherein the second epitaxy region comprises a second lower portion having the first doping concentration of the conductive type, and a second upper portion having a third doping concentration of the conductivity type, and the third doping concentration is higher than the first doping concentrate, and wherein a second inner edge of the second upper portion is spaced apart from a second outer edge of the second gate spacer; and a second source/drain silicide region over and contacting the second epitaxy region, wherein the second source/drain silicide region has a third inner edge flushed with the second inner edge of the second upper portion.
 11. The structure of claim 10, wherein the second epitaxy region further comprises a third upper portion over the second lower portion, wherein the third upper portion is closer to the second gate spacer than the second upper portion, and the third upper portion has a lower doping concentration than the third doping concentration.
 12. The structure of claim 10, wherein the conductive type is p-type.
 13. The structure of claim 10, wherein the conductive type is n-type.
 14. The structure of claim 10, wherein the first transistor has a longer channel than the second transistor.
 15. The structure of claim 10, wherein the first transistor and the second transistor are Fin Field-Effect Transistors (FinFETs).
 16. A structure comprising: a first transistor comprising: a first gate stack; a first gate spacer on a sidewall of the first gate stack; and a first source/drain region on a side of the first gate stack, wherein the first source/drain region is laterally spaced apart from the first gate stack by a first distance; and a second transistor comprising: a second gate stack; a second gate spacer on a sidewall of the second gate stack; and a second source/drain region on a side of the second gate stack, wherein the second source/drain region is laterally spaced apart from the second gate stack by a second distance greater than the first distance, and the first source/drain region and the second source/drain region are of a same conductivity type.
 17. The structure of claim 16, wherein the first transistor has a first channel length, and the second transistor has a second channel length smaller than the first channel length.
 18. The structure of claim 17, wherein the first channel length is more than twice the second channel length.
 19. The structure of claim 16, wherein the first distance is equal to or smaller than a first thickness of the first gate spacer, and the second distance is greater than a second thickness of the second gate spacer.
 20. The structure of claim 16 wherein the first gate spacer comprises: a first layer formed of a low-k dielectric material; and a second layer spaced apart from the first gate stack by the first layer, wherein the second layer is formed of a non-low-k dielectric material. 